Cache Memory Design for Internet Processors

The exponential growth in Internet popularity motivates network router and switch designers to develop custom software/hardware that can move packets through the network faster. Recently, a new breed of microprocessors called Internet processors have come into existence speciically to address the performance problem due to exploding In-ternet traac. The development eeorts of these Internet processors concentrate almost exclusively on streamlining their data-paths to speed up network packet processing, mainly routing and data movement. As higher-level protocol processing functionality is shifted towards network devices, e.g., the active network architecture, Internet processors are required to perform more sophisticated tasks at ever higher speeds. Rather than blindly pushing the performance of packet processing hardware, an alternative approach is to avoid repeated computation by applying the time-tested architectural idea of caching to network packet processing. Because the data streams presented to Internet processors and Internet processors and general-purpose CPUs exhibit diierent characteristics, detailed cache design tradeoos for the two also diier considerably. This research represents one of the rst, if not the rst, reported works that focus on cache memory design speciically for Internet processors. Using a trace-driven simulation methodology, we evaluate a series of three progressively more aggressive routing-table cache designs, and a lter cache design that supports general packet ltering for re-walling and packet classiication. Our simulation results demonstrate that the incorporation of hardware caches into Internet processors can signiicantly improve the overall packet forwarding performance due to a suuciently high degree of temporal locality in the network packet streams, and diierent cache designs can result in up to a factor of 4 diierence in overall packet forwarding rates.